---
name: gplcver
version: 2.12.a
origin: cad/gplcver
comment: A Verilog HDL simulator
arch: freebsd:9:x86:64
www: http://sourceforge.net/projects/gplcver/
maintainer: ports@FreeBSD.org
prefix: /usr/local
licenselogic: single
flatsize: 1560624
desc: |
  GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also
  implements some of the 2001 P1364 standard features including all three
  PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language
  Reference Manual (LRM).

  Verilog is the name for both a language for describing electronic hardware
  called a hardware description language (HDL) and the name of the program
  that simulates HDL circuit descriptions to verify that described circuits
  will function correctly when the are constructed. Verilog is used only for
  describing digital logic circuits. Other HDLs such as Spice are used for
  describing analog circuits. There is an IEEE standard named P1364 that
  standardizes the Verilog HDL and the behavior of Verilog simulators.
  Verilog is officially defined in the IEEE P1364 Language Reference
  Manual (LRM) that can be purchased from IEEE. There are many good books
  for learning that teach the Verilog HDL and/or that teach digital circuit
  design using Verilog.

  WWW: http://sourceforge.net/projects/gplcver/
categories: [cad]
files:
  /usr/local/bin/cver: 85c1706e2e99d7ef05789d8b8dd646a463d010252896d507ec0f2bd482e264c5
scripts: {}
